Many modern electronics applications use high-performance central processing units (CPUs). In such contexts, achieving high performance can rely on obtaining high data bandwidth from the CPU. Typically, design constraints on CPUs have limited increases in physical size and pin count of CPUs. Accordingly, meeting ever-increasing demands for data bandwidth has involved designing CPUs with ever-increasing input/output (I/O) data rates. As an example, the Infini-band Enhanced Data Rate standard (IB EDR) exceeds 25 Gigabits per second.
Achieving such I/O data rate increases can be difficult. For example, each I/O location (e.g., pin) on the CPU can have a serializer/deserializer (SERDES) with a receiver and a transmitter, and increasing the I/O data rate can rely on increasing the SERDES operating speed. The SERDES transmitter typically includes a transmitter driver that prepares output data for transmission over a high-speed channel. Effective operation of a transmitter driver at high data rates can depend on the driver continuing to meet high performance requirements, such as high bandwidth, high finite impulse response (FIR) range, fine resolution, low jitter, and low duty cycle distortion (DCD).